NCP1083DEG【PDF 16/18 页】IC CONV CTLR POE-PD 40W 20-TSSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录45

12页 13页 14页 15页 [16页]17页 18页

NCP1083

http://onsemi.com

Both VDDH and VDDL regulators turn on as soon as

VPORT reaches the Vuvlo_on threshold.

Error Amplifier

In nonisolated converter topologies, the high gain

internal error amplifier of the NCP1083 and the internal

1.2 V reference voltage regulate the DCDC output voltage.

In this configuration, the feedback loop compensation

network should be inserted between the FB and COMP pins

as shown in Figures 3, 4 and 5.

In isolated topologies the error amplifier is not used

because it is already implemented externally with the shunt

regulator on the secondary side of the DCDC controller

(see Figure 2). Therefore the FB pin must be strapped to

ARTN and the output transistor of the optocoupler has to

be connected on the COMP pin where an internal 5 kW

pullup resistor is tied to the VDDL supply (see Figure 16).

SoftStart

The softstart function provided by the NCP1083 allows

the output voltage to ramp up in a controlled fashion,

eliminating output voltage overshoot. This function is

programmed by connecting a capacitor C

between the SS

and ARTN pins.

While the DCDC controller is in POR, the capacitor C

is fully discharged. After coming out of POR, an internal

current source of 5 mA typically starts charging the capacitor

to initiate softstart. When the voltage on SS pin has

reached 0.45 V (typical), the gate driver is enabled and

DCDC operation starts with a duty cycle limit which

increases with the SS pin voltage. The softstart function is

finished when the SS pin voltage goes above 1.6 V for which

the duty cycle limit reaches its maximum value of 80

percent.

Softstart can be programmed by using the following

equation:

(ms) + 0.23 C

(nF)

Current Limit Comparator

The NCP1083 current limit block behind the CS pin

senses the current flowing in the external MOSFET for

current mode control and cyclebycycle current limit. This

is performed by the current limit comparator which, on the

CS pin, senses the voltage across the external Rcs resistor

located between the source of the MOSFET and the ARTN

pin.

The NCP1083 also provides a blanking time function on

CS pin which ensures that the current limit and PWM

comparators are not prematurely trigged by the current spike

that occurs when the switching MOSFET turns on.

Slope Compensation Circuitry

To overcome subharmonic oscillations and instability

problems that exist with converters running in continuous

conduction mode (CCM) and when the duty cycle is close

or above 50 percent, the NCP1083 integrates a current slope

compensation circuit. The amplitude of the added slope

compensation is typically 110 mV over one cycle.

As an example, for an operating switching frequency of

250 kHz, the internal slope provided by the NCP1083 is

27.5 mV/ mA typically.

DCDC Controller Oscillator

The frequency is configured with the Rosc resistor

inserted between OSC and ARTN, and is defined by the

following equation:

OSC

(kW) +

38600

OSC

(kHz)

The duty cycle limit is fixed internally at 80 percent.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式